87 lines
3.0 KiB
ArmAsm
87 lines
3.0 KiB
ArmAsm
format elf64
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section '.text' executable
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; Details on Control Registers and MSRs can be found here:
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; https://wiki.osdev.org/CPU_Registers_x86-64
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; x64fastcall void paging_modeswitch_4LevelPaging(void* pml4, int pcid)
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;
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; This function assumes that the program is now in 64-bit mode (long mode).
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; Paging(CR0.PG) in general and long mode (MSR EFER.LME) must already be enabled in this state.
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;
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; Input: (void* rcx, int rdx)
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; Clobbers: rax, flags
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public paging_modeswitch_4LevelPaging
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paging_modeswitch_4LevelPaging:
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; 4 Level paging: CR0.PG (bit 31) = 1 (Protected mode enable)
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; CR4.PAE (bit 05) = 1 (PAE enable)
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; MSR IA32_EFER.LME (bit 10) = 1 (IA32e 64-bit mode enable)
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; CR4.LA57 (bit 12) = 0 (4-level paging instead of 5)
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; We only need to set CR4.LA57
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; Let's also set CR4.PCIDE(bit 17)=1, enabling process-context identifiers
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mov rax, cr0
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and rax, 0xFFFFFFFFFFFFEFFF ; unset CR4.LA57
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or rax, 0x20000 ; set CR4.PCIDE
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mov cr0, rax
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and rdx, 0xFFF ; take only the 11:0 bits of the PCID
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or rcx, rdx ; construct the full CR3
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mov cr3, rcx ; set CR3, invalidate all TLB cache
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ret
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; x64fastcall void paging_modeswitch_4LevelPagingNX(void* pml4, int pcid)
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;
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; This function assumes that the program is now in 64-bit mode (long mode).
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; Paging(CR0.PG) in general and long mode (MSR EFER.LME) must already be enabled in this state.
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;
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; This function also sets the IA32_EFER.NXE bit, enabling No-Execute feature.
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;
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; Input: (void* rcx, int rdx)
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; Clobbers: rax, r8, r9, flags
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public paging_modeswitch_4LevelPagingNX
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paging_modeswitch_4LevelPagingNX:
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; 4 Level paging: CR0.PG (bit 31) = 1 (Protected mode enable)
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; CR4.PAE (bit 05) = 1 (PAE enable)
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; MSR IA32_EFER.LME (bit 10) = 1 (IA32e 64-bit mode enable)
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; CR4.LA57 (bit 12) = 0 (4-level paging instead of 5)
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; We only need to set CR4.LA57
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; Let's also set CR4.PCIDE(bit 17)=1, enabling process-context identifiers
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mov rax, cr0
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and rax, 0xFFFFFFFFFFFFEFFF ; unset CR4.LA57
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or rax, 0x20000 ; set CR4.PCIDE (bit 17)
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mov cr0, rax
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; save rcx and rdx, RDMSR/WRMSR uses these
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mov r8, rcx
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mov r9, rdx
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mov ecx, 0xC0000080 ; operate on the IA32_EFER MSR
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rdmsr ; read the MSR into edx:eax
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or eax, (1 shl 11) ; set No-Execute Enable (bit 11)
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wrmsr ; write the MSR back
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; restore rcx and rdx
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mov rcx, r8
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mov rdx, r9
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and rdx, 0xFFF ; take only the 11:0 bits of the PCID
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or rcx, rdx ; construct the full CR3
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mov cr3, rcx ; set CR3, invalidate all TLB cache
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ret
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; x64fastcall void paging_modeswitch_Table(void* pml, int pcid)
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;
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; This function simply sets CR3 and run INVLPG, flushing the TLB cache.
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;
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; Input: (void* rcx, int rdx)
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; Clobbers: none
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public paging_modeswitch_Table
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paging_modeswitch_Table:
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and rdx, 0xFFF ; take only the 11:0 bits of the PCID
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or rcx, rdx ; construct the full CR3
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mov cr3, rcx ; set CR3, invalidate all TLB cache
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ret
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